In the digital design world, we have typically only seen S-parameters used to model packages. They are a popular output of 3D field solvers like IE3D. But more and more, especially in SERDES design, we are seeing S-parameters being used for a variety of parts. One of the reasons for their growing popularity is their fater simulation time, especially when advanced simulation techniques are used, as in the case of Mentor’s complex-pole fitting in HyperLynx and ELDO.
S-parameters are also used to model connectors, and even entire interconnects. In fact, it is often a good idea to extract an S-parameter for your entire interconnect, including any packages and connectors. This allows you to view the interconnect as one S-parameter, and look at data like the total loss across the interconnect. Many industry standard SERDES busses like PCI Express and Serial ATA specify a maximum total insertion loss through an interconnect. As such, comparing your total insertion loss from the channel S-parameter to that loss spec gives you an excellent indication of the performance of your link without having to run a long simulation. Of course, to really see the benefits of things like pre-emphasis and equalization to overcome channel losses, you should run some kind of time-domain simulation with your buffer models. FastEye in HyperLynx can really speed that up.
For more information on recent developments in SERDES simulation, take a peek at my recent article in PCD&F:
http://pcdandf.com/cms/component/content/article/171-current-issue/7704-designers-notebook